CMP_COMP_REG1

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Interpret as CMP_COMP_REG1

COMP_HS0_HYST=Val_0x0, COMP_HS0_IN_M_SEL=Val_0x0, COMP_HS0_IN_P_SEL=Val_0x0, COMP_HS1_HYST=Val_0x0, COMP_HS1_IN_M_SEL=Val_0x0, COMP_HS1_IN_P_SEL=Val_0x0

Description

Comparator Register 1

Fields

COMP_HS0_IN_P_SEL	Selects input to positive terminal of CMP0: 0 (Val_0x0): CMP0_IN0 pin 1 (Val_0x1): CMP0_IN1 pin 2 (Val_0x2): CMP0_IN2 pin 3 (Val_0x3): CMP0_IN3 pin
COMP_HS0_IN_M_SEL	Selects input to negative terminal of CMP0: 0 (Val_0x0): VREF_IN0 pin 1 (Val_0x1): VREF_IN1 pin 2 (Val_0x2): Internal Vref 3 (Val_0x3): DAC6
COMP_HS0_HYST	Sets CMP0 hysteresis level. 6-mV steps 0 (Val_0x0): 0 mV 7 (Val_0x7): 45 mV
COMP_HS1_IN_P_SEL	Selects input to positive terminal of CMP1: 0 (Val_0x0): CMP1_IN0 pin 1 (Val_0x1): CMP1_IN1 pin 2 (Val_0x2): CMP1_IN2 pin 3 (Val_0x3): CMP1_IN3 pin
COMP_HS1_IN_M_SEL	Selects input to negative terminal of CMP1: 0 (Val_0x0): VREF_IN0 pin 1 (Val_0x1): VREF_IN1 pin 2 (Val_0x2): Internal Vref 3 (Val_0x3): DAC6
COMP_HS1_HYST	Sets CMP1 hysteresis level. 6-mV steps 0 (Val_0x0): 0 mV 7 (Val_0x7): 45 mV
COMP_HS_EN	Enables High-Speed comparators: Bit 29: CMP1 enable Bit 28: CMP0 enable

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